1. Field of the Invention:
The present invention relates generally to semiconductor integrated circuits, and more specifically to test circuitry for use on programmable logic devices.
2. Description of the Prior Art:
Programmable logic devices are increasingly being used in the electronics industry. These devices can be easily programmed by a purchaser to perform many different simple to moderately complex logic functions for inclusion in electronic systems. Programmable logic devices may be one time programmable, or may be reprogrammable by the user.
One type of programmable logic device utilizes a programmable AND/OR array to perform logic functions. Inputs and their complements are provided as row inputs to the array, and product terms are generated as outputs therefrom. The array is typically provided as a matrix, and connections are made between the various input rows and product term lines in order to define logic functions. The provision of input signals to the array and handling of the product term outputs are well known in the art.
A typical programmable logic device of the type described above can have, for example, 22 inputs, resulting in 44 rows provided to the array. Such a typical device can also have, for example, 132 product terms. As known in the art, a bit map describing the programming of each cross-point in the array, referred to as a JEDEC bit map, is typically generated to provide data for programming the device. The data from the bit map is shifted into the programmable logic device one row at a time in order to program the rows. A serial shift register is provided on the device for such purpose.
During testing of a reprogrammable programmable logic device, it is desirable for the manufacturer to write several test patterns into the device to insure that all of the memory elements in the array are functioning properly. These patterns typically include all ones, all zeros, alternating stripes of ones and zeros, and alternating ones and zeros in a checkerboad pattern. True and inverted checkerboard and striped patterns are typically generated, giving six basic test patterns used to test the device. In order to speed up the writing of these regular test patterns, it is known in the art to simultaneously select alternate rows within the array, typically referred to as odd or even rows, and write the same data into each of these selected rows at the same time.
Many different integrated circuit technologies are used to provide the memory elements in the array for such programmable logic devices. Various types of EPROM and EEPROM cells are in common use. SRAM devices are becoming popular due to their speed and ease of programming. With the exception of SRAM based devices, programming these devices takes a relatively long time, on the order of hundreds of milliseconds. Using technologies other than SRAM, the time taken to serially shift the programming bit map into and out of the device, typically hundreds of microseconds, is an insignificant part of the programming time. However, the programming time for SRAM based devices is typically a few hundred nanoseconds, and the hundreds of microseconds required to shift data onto and off of the device dominates the programming time.
It would be desirable to provide a programmable logic device, such as a device using an SRAM technology for storing the program data, which minimizes the programming time required for the chip. It would be desirable for such a technique to provide an overall programming time which is approximately the same as the time required to program the test data into the device, and eliminating the time required to shift the programming data onto and off of the device.